The Museum of HP Calculators
The Museum of HP Calculators
The classic series used a multichip CPU. The Control and Timing (C&T) chip performed all the major nonarithmetic functions. It polled the keyboard, tracked system status and generated instruction addresses sent to the ROM. The C&T chip provided a word select feature which allowed the A&R chip (below) to operate on partial words (for example the exponent field) separately.
The Arithmetic and Register (A&R) chip contained 7 56 bit (14 BCD digits) registers. Three of these registers were the X, Y, and Z registers of the four level stack. Two more were working registers and one was the user-visible memory register (STO/RCL.) The final register did double duty as the topmost register in the stack (T) and as a working register for trigonometric functions. Thus when a trig function was used, the topmost value in the stack was lost. The A&R chip also contained instruction decoding circuits, a decimal adder-subtractor and a display decoder.
The calculator used digit-serial, bit-serial organization to reduce size, cost and increase reliability. This serial design also made the word select feature easier to implement. The A&R chip responded to a word select signal from the C&T chip as the appropriate part of the number passed serially through it. HP designed the logic and most of the chips were manufactured by outside vendors such as Mostek.
The classic series machines used ROM chips which contained 256 instructions of 10 bits each. The number of ROMs used varied by machine (for example, three in the HP-35 and seven in the HP-80.) ROM chips respond to addresses and word select signals from the C&T chip.
Special LED clusters were developed by HP because existing LEDs consumed too much power and were too expensive. The LEDs were grouped into 5 decimal digits into a single 14 pin DIP with magnifying lenses over each digit.
The classic series machines where built with two circuit cards supported by a plastic "backbone". The larger card contained the key contacts and the LEDs and LED drivers and the smaller card contained the (A&R), (C&T) ROMs, and other components.
Picture of an HP-35 CPU board. (~60K)
Picture of an HP-45 CPU board. (~55K)
Picture of keyboard contact/LED board,
front case, key bracket, membrane and some keys. (~42K)
Picture of an HP-55 CPU board. (~60K)
Picture of an HP-55 CPU board on "backbone". (~42K)
Picture of an HP-65 interior. (~52K)
Picture of an HP-65 CPU board. (~49K)
Picture of an HP-65 card reader from the back. (~43K)
Picture of the HP-65 card reader switches (start/stop,
write protect etc). (~16K)
Picture of an HP-65 top case from inside showing how the
on/off, and top-row legends are molded through. (~35K)
Picture of an HP-70 CPU board. (~37K)
Picture of an HP-80 CPU board. (~47K)
Producing accurate answers for transcendental functions on a very small/slow computer was no simple task. HP considered power series, Chebyshev polynomials, polynomial expansions, and continued fractions but all were too slow due to the number of divisions and multiplications needed. The algorithm chosen was an iterative pseudo-division/pseudo-multiplication method first described in 'Arithemtica Logarithma' in 1624 by Henry Briggs. Because of the complexity of the programs, a subroutine capability and a set of status flags was built into the chip set.
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